Instruction Set

As of 2nd November 1995
by John Cleary

Block

Each block consists of 16 slots.(16x2 = 32 words = 128 bytes)

Slot

Each slot has as input an I (instruction) word of 32 bits and a C (constant) word of 32 bits.

An active slot has four fields. An F-field (24 bits), and two registers R1 and R2 (each of 32 bits) and a 1-bit S(elect) register.

C-word

The C-word is always treated as a single 32-bit value, it is stored in one of the registers of its associated slot or the next lowest numbered slot.

I-word contains:

CC (3 bits)

This controls where the C-word is sent and optionally sets R1 or R2 to 0.

000 - ignore C-word.
001 - R1=C send C-word to register R1 of this slot.
010 - R2=C
011 - R2'=C send C-word to register R2 of the precedeing slot.
100 - R1=0, R2=C.
101 - R2=0, R1=C.
110 - R1=0, R2'=C.
111 - R2=0, R2'=C.

Op - (5 bits)

op code - address of functional unit to which contents of active slot are sent. Opcodes 0..15 use their low order bit,SC, to control the use of the S-register (so only 8 op-codes are effectively available in this range). 0 indicates to wait for the S- register to be set before firing, 1 means to initially set the S-register (it may be reset later). (NOP is achieved by using SC=0 and never setting it).

F - (24 bits)

Transmitted as is to the functional unit. Interpretation depends on particular functional unit.

Transmission from active slot to functional unit consists of:
Op - (5 bit address)
F - (24 bits)
R1 - (32 bits)
R2 - (32 bits)
Total - 93 bits.

Assembler notation

Register contents:

A - 32 bit address.

V - 32 bit value (uninterpreted).

F - 32 bit floating point value.

F-subfields

(n) - n bits in field.
xm - duplicated m times (numbered 1..m)

Typical subfields include:
d(6) - destination register - specifies register and slot within current block. 0..15 are ignored, 16-31 refer to S-registers 0..15, and 32-63 refer to Registers 0 to 31 (adjacent even/odd pairs occur in the same slot).

cop(3) - comparison suboperator - useful values are, lt, leq, gt, geq, eq, neq.

sop(2) - split operator, see split instruction.

c1(2) - 2 bit specifier of child ranging over 0,1,2,3

Instruction Set

No.
Op     R1  R2  F-field

Description

Time Manipulation

0&8
?CHILD A1  A2  c1(2) mi(2) ds(16)
Execute child c1 at address (A1), using A2 as migration hint (0 is a null that supplies no hint). mi specifies how migration is to be treated: 00 - don't migrate; 01 - migrate only if no free frames on local machine; 10 - migrate optionally ; 11 - always migrate to different machine. The ds field specifies a 16 bit mask, 1 bit for each slot in the frame. If a bit is on then a child will set both the S-register for that slot and send a CR word to the second register.
1&9
?TRAP  V1  V2  con(24)
trap to operating system at a time just after current block and before any children. V1, V2 and con are available to the operating system, all children after this time are stored to memory (?many details need sorting out here).

Memory Operations

2&10
?ST    V1  A2  a(24)
Store V1 at address (A2+ax4) (just after current time).
3&11
?MV    V1  CR2 d(6)
Store value V1 into destination register d of child referred to by CR2.
4&12
?MA    A1  CR2 d(6) a(18)
Load value at address (A1+4xa) at time just before execution of child referred to by CR2 into destination d of child referred to by CR2.

Comparison

16
CMP    V1  V2  cop1(3)d1..2(6) 
               cop2(3)d3(6)
 Compare V1 and V2 using cop. The result of cop1 is sent to d1 and its complement to d2. The result of cop2 is sent to d3.

Integer Arithmetic

17
ADD    V1  V2  d1..4(6)
Add V1 and V2. Move sum to d1..3 and overflow to d4.
18
SUB    V1  V2  d1..4(6)
Subtract V2 from V1. Move difference to d1..3 and overflow to d4.
19
MUL    V1  V2  d1..4(6)
Multiply V1 by V2 move the low order 32 bits of the result to d1..3 and the high order 32 bits to d4.
20
DIV    V1  V2  d1..4(6)
Divide V1 by V2. Move integer part of the result to d1..3 and the remainder to d4.
21
SPLIT  V1  V2  (sop(2)d(6))x3
Divide the word V1, about bit b=(V2 mod 32). Each sop contains two bits. The first says whether the left or right part of the word is being referenced, the second says whether that part is to be justified left or right in the result.

Floating Point Arithmetic

22
ADDF   F1  F2  d1..4(6)
Add F1 and F2. Move sum to d1..4.
23
SUBF   F1  F2  d1..4(6)
Subtract F2 from F1. Move difference to d1..4.
24
MULF   F1  F2  d1..4(6)
Multiply F1 by F2 move the move the result to d1..4.
25
DIVF   F1  F2  d1..4(6)
Divide F1 by F2. Move the result to d1..4.
26
F2I    F1  F2  d1..4(6)
Divide F1 by F2. Move the integer part of the result to d1..2 (as a 32-bit integer) and the fractional part (as a floating point number) to d3..4.
27
I2F    V1  V2  d1..4(6)
Multiply the (integers) V1 and V2, convert the result to a float (avoiding loss of precision as far as possible) and send the result to d1..4.

Logic

28
AND    V1  V2  d1..4(6)
Take bitwise AND of V1 and V2 and move result.
29
OR     V1  V2  d1..4(6)
Take bitwise OR of V1 and V2 and move result.
30
XOR    V1  V2  d1..4(6)
Take bitwise XOR of V1 and V2 and move result.

Notes:

All effective memory addresses must have low order 2 bits = 0.

Child reference values (CR) can be passed around the system with the proviso that they are always passed into the future of the child they refer to. They can thus be used remotely as a target of an ST (a zero is always a null CR).

It is allowed (and will be efficient) to store into the constants of a block (it is NOT permitted to store into an actual instruction). This can be used to distribute parameters to loops for example (but be careful it won't be re-entrant).

The Structure of Time:

A child is allocated a time range this is further subdivided as follows (using binary fractions):
000page faults for incoming MA messages. Actually 000000000 to 000111111 with one time slot for each possible destination using the usual destination numbering. 000000000 is reserved for the page fault corresponding to fetching the code and 000000001 to 000001111 are reserved for other uses.
001time at which execution occurs.
010reserved.
011instruction faults. Actually 0110000 to 0111111 with one for each slot in the frame.
100child 0.
101child 1.
110child 2.
111child 3.