Block Based Execution and Task Level Parallelism

Richard H. Littin, J. A. David McWha,
Murray W. Pearson and John G. Cleary

Department of Computer Science,
University of Waikato,
Hamilton, New Zealand
{rhl, jadm, mpearson, jcleary}@cs.waikato.ac.nz

Abstract:

A fixed-length block-based instruction set architecture (ISA) based on dataflow techniques is described. This ISA is the compared and contrasted to those of more conventional architectures and other developmental architectures. A control mechanism to allow blocks to be executed in parallel, so that the original control flow is maintained, is presented. A brief description of the hardware required to realize this mechanism is given.

 
• Introduction
• Architecture Evolution
• Speculation with BSA
• Block control
• Architecture
• Experimental Framework
• Results
• Conclusions
• References
• About this document ...

In Proceedings of Australasian Computer Architecture Conference (ACAC'98), University of Western Australia, Perth, Australia, 2-3 February, 1998