1. The Architecture of an Optimistic CPU: The WarpEngine.
   1. Abstract
   2. 1. Introduction
   3. 2. TimeWarp
   4. 3. Time-stamped Memory
      1. 3.1.Implementation of the Time-stamped Memory
      2. 3.2. Inter-processor Communication
      3. 3.3. Size of the Time-space Cache
   5. 4. Code Blocks and Time stamps
   6. 5. GVT Calculation
   7. 6. Instructions
      1. 6.1. Instruction Execution
      2. 6.2. Individual Instructions
      3. 6.3. Execution Rollback
   8. 7.The Hardware Structure of the WarpEngine CPU
   9. 8. Estimated Performance
   10. 9. Summary and Future Work
   11. Acknowledgments
   12. References