Theses
			R. Littin (2000) Design and Evaluation of an Optimistic CPU: The WarpEngine, PhD thesis, University of Waikato, Hamilton, New Zealand. (abstract)
Papers
2000
			J. Cleary, R. Littin, D. McWha, M. Pearson (2000) Scaling the Reorder Buffer to 10,000 Instructions, To appear in IEEE Computer Society Technical Committee for Computer Architecture Newsletter
			J. Cleary, R. Littin, D. McWha, M. Pearson (2000) Scaling the Reorder Buffer to 10,000 Instructions?, (Extended abstract) In High-Performance Computer Architecture - Work In Progress Session (HPCA-WIP), 10-12 January, 2000, Centre de congres Pierre Baudis, Toulouse, France
1999
			Littin R. H. (1999) Data and control speculative execution, In proceedings of the 3rd New Zealand Computer Science Research Students' Conference (NZCSRSC'99), 6-9 April, 1999, University of Waikato, Hamilton, New Zealand Also to appear in the New Zealand Journal of Computing
			McWha J. A. D. (1999) Using Timestamps to Maintain Causal Dependencies, In proceedings of the 3rd New Zealand Computer Science Research Students' Conference (NZCSRSC'99), 6-9 April, 1999, University of Waikato, Hamilton, New Zealand
			Cleary J. G., Littin R. H., McWha J. A. D. and Pearson M. W. (1999) Space Constraints on High Levels of ILP, In proceedings of 4th Australasian Computer Architecture Conference (ACAC'99), 18-20 January, 1999, Auckland, New Zealand Supercedes working paper 97/27
1998
			Littin, R.H., McWha, J.A.D., Pearson, M.W. & Cleary, J.G. (1998) Block Based Execution and Task Level Parallelism, In proceedings of 3rd Australasian Computer Architecture Conference (ACAC'98), 2-3 February, 1998, Perth, Australia
1997
			Cleary J. G., Littin, R. H., McWha, J. A. D. & Pearson M. W. (1997) Constraints on Parallelism Beyond 10 Instructions Per Cycle, working paper 97/27, Dept. Computer Science, University of Waikato.
			Littin, R. H. & Cleary J. G. (1997) Effects of Re-ordered Memory Operations on Parallelism, working paper 97/28, Dept. Computer Science, University of Waikato.
			Pearson, M.W., Littin, R.H., McWha, J.A.D. & Cleary, J.G. (1997) Applying Time Warp to CPU Design,In proceedings of High Performance Computing Conference, 18-21 December, 1997, Bangalore, India
			Cleary, J.G., McWha, J.A.D. & Pearson, M. (1997) Timestamp Representations for Virtual Sequences, In proceedings of 11th Workshop on Parallel and Distributed Simulation (PADS'97), 10-13 June, 1997, Lockenhaus, Austria Supercedes working paper 96/27
1996
			Cleary, J.G., McWha, J.A.D. & Pearson, M. (1996) Timestamp Representations for Virtual Sequences, working paper 96/27, Dept. Computer Science, University of Waikato.
1995
			Cleary, J.G., Pearson, M.W. & Kinawi, H. (1995) The Architecture of an Optimistic CPU: The Warp Engine, Proc. HICSS'95, vol 1. pp 163 - 172.
Presentations
1999
			Richard Littin (1999) Data and control speculative execution, Presented at the 3rd New Zealand Computer Science Research Students' Conference (NZCSRSC'99), 6-9 April, 1999, University of Waikato, Hamilton, New Zealand
			Richard Littin (1999) Space Constraints on High Levels of ILP, Presented at the 4th Australasian Computer Architecture Conference (ACAC'99), 18-20 January, 1999, Auckland, New Zealand
1998
			Richard Littin (1998) Block Based Execution and Task Level Parallelism, Presented at the 3rd Australasian Computer Architecture Conference (ACAC'98), 2-3 February, 1998, Perth, Australia