Dean gave an update on how his SimpleScalar based simulator for the MIPS/WarpEngine is going. There is a minor bug left, but it should be worked out within a week, and then the single processor version of the simulator will be operational. It does full rollback and re-execution due to out-of-order memory accesses. This is probably the hardest part, and it should now be easy to extend to multiple processors (superframes). All memory accesses are bytes, because it is difficult to handle retiring variable sized memory accesses, padding to a whole byte may overwrite allocated memory.
Murray then gave a review of his initial design of a timespace cache from a few years ago. As it is essentially a big ordered array it generates vast amounts of heat each operation as the array is shifted to reorder the entries. David will consider more intelligent schemes, such as splitting the list by load/store, and by address. Hashing may provide a way to access the list more efficiently.
David is currently putting on paper what he plans to do for the next 6 months to (hopefully!) finish his PhD. This means simulating the time space cache using the transient simulator and doing a detailed design of the timestamp matching unit.
We forgot to tell Dean the meeting was on, so he will tell us about his simulator next week.
The single CPU version executes one thread at a time, when a fork occurs it pushes both new forks onto the stack and pops the top one off for execution. The single CPU operates essentially like an ordinary OOO superscalar CPU, with a large reorder buffer, and time-space memory. When multiple CPUs are used more than one thread can be popped off the stack
The simulator executes rather slowly, particularly the multi-CPU version. To speed this up Dean will work on removing list scanning that goes on, particularly in checking for ready instructions in the ROB, in calculating GVT and in memory, which is currently a linked list (by address) of linked lists (multiple versions of memory accesses). The memory model will be changed to an array, to allow faster accessing. Currently fork instructions stall until they are the GVT holder, ie non-speculative. This is only a small inaccuracy for the single CPU model, but for multi-CPUs it restricts it to 2 threads (and CPUs) - this is not good! IO will be done using a TRAP instruction which executes when it becomes GVT holder (non-speculative). Time stamping should be done on CPU id, not thread id. He will also work on putting David's resource estimation work into the simulator, to allow multiple threads to be assigned to a single CPU in parallel.
Oh, yes, Richard has finished his PhD. Look out for the amended version (following examiners comments) to appear on a web page near you soon! He has now left the university and is working for the Intelligenesis branch in Hamilton. His New Zealand examiner made some suggestions for papers to write from his thesis too, so watch out for those also.
Dean was working on the real time simulator for the MIPS-based WarpEngine. He got that essentially working for a single thread of control, and was spending the last couple of months optimising performance. He has now finished his employment, and isn't likely to do any more work on it, since he has an (unrelated) honours project to worry about.
Richard has got his corrections finished to his PhD thesis and has had it bound and submitted. He is finished, congratulations Richard! I will be (hopefully) putting up an electronic copy soon for download.
David has fixed the simulator to take account of transient memory accesses (rather than just the correct access), which Richard had written, but never used. There were a number of very subtle bugs in it. Use of resource blocks to restrict parallelism (only a fixed number of events requiring unknown resources can execute in parallel) can now be simulated. Unfortunately it is rather slow (due to the amount of state kept) and results are still being collected.
He is frantically trying to get some simulation done of the twisted memory structure for the Time-Space cache. He has a job starting in Australia in March 2001, so he will have to stop soon and focus on writing up his thesis.
Bill's work on the compiler seems to have stalled as more interesting research projects have come up. John and Murray have really only been contributing suggestions on the other work at group meetings, as they too focus on other research.
From this point onwards there is likely to be little of interest from the meeting, once David has some twisted memory results.
If you are interested in the project, and want to discuss it, or even participate, there are still plenty of open questions, so email me.